Cache Misses
sum of three is Total Cache Miss Count (3C's model)
- compulsory cache misses (cold miss) always occur since cache is assistant memory
occur count: only bone miss per used line
line is in memory so occur for only used block
- capacity cache misses occur by cache size
occur count: reload miss by small total cache size
only occur there is comp size bigger than cache size
out before least recently used than other
- conflict cache misses occur by the way in set; if lines in same set(do not occur with full associativity)
occur count: thrashing
will never occur in fully associative LRU, so assumed fully LRU their is no miss and not compulsory miss then it is capacity miss
캐시미스 때문에 메모리 중요하면 linked-list(memory-oriented) 성능 중요하면 배열로(time-oriented)