Instruction Dependency

Creator
Created
Created
2019 Nov 5 5:17
Editor
Edited
Edited
2023 Feb 28 15:55
Refs
Refs
dependency is kind of hazard, dependency could be a datas hazard. actual hazard and any length of stall is a property of pipeline(parallel processing)
  • dependency determine order in which results must be calculated
  • dependency set has upper bound on how much parallelism can possibly he exploited
 
Basic block : instruction block between control instruction(ex. branch, jump) fetch : take instruction memory dispatch : throw instruction to FU Squash : early end instruction which do not have all stage
hardware trade-off(compete) between price and performance

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