Seong-lae Choall is about mips
Dependency
output dependency = WAW
load change memory and store change register - L1L2 cache solve that
anti-dependency (not occur in simple pipe line (no OoO scheduling))
Data forwarding
three stall to dm load type
two stall to alu r type
but by forwarding
like chaining at vector processor
two stall two 0
mem/wr → ID/EX
EX/MEM → ID/EX
one stall to 0
(memoryto-memory copies)
load store - 2(half write half read) to 0 stall
load use 2(half write half read) to 1 stall
stall the pipeline means DM final to ALU first
load use can be 2 stall since pre half cycle write and after half cycle read
Control hazerd
jump 1
branch 3 always if no branch predict
breanch forwarding
3stall with no branch prediction
2 flush with brench prediction false (at branch execution)
resource conflict is structural hazard Procedural Dependency is by branch or jump