Seong-lae Cho- Local miss rate = misses in cache / access cache
- Global miss rate = misses in cache / CPU memory accesses
- L1 Instruction Cache
has large block size
to increase spatial locality
- L1 Data Cache
this split structure enable independent access
parallel multi-ported register file (part of CPU)
- Unified L2 Cache
let L1 smaller and write-through L1, write back L2
All caches are on chip SRAM and memory is off-chip DRAM
Inclusive multilevel cache
Exclusive multilevel caches
level 1 data is in level 2
level 1 data is not in level 2
Inclusive is usual but exclusive used as below
swap lines between inner/outer caches on miss