Seong-lae ChoIncrease page level to reduce page table
kernel address is accessible from both direction
Each Process has Page Table, Page table entry(PTE) has valid, access bit
Page Table Arguments
- V = {0 ,1 , ..., N-1}: virtual address space
- P = {0, 1, ..., M-1}: physical address space
- N > M: difference that not comparable
- MAP: V → P U {null} address mapping function
- null if in Disk (if valid is 0): page fault
Page Table Parameters
log upper = lower
- P = Page size (bytes): typically KBs
- N = Virtual Address limit
- M = Physical address limit
virtual address = virtual page number(VPN) bit + page offset
VPN acts page index in page table
physical address = physical page number bit + page offset
address translation change previous one only (32 bit to other)
compare start by page table base register
page table need protection and cache do not need because of address translation