Seong-lae Cho- All three status is scoreboard and hardware fixed which has logical structure
- functional unit status are book keeping in scoreboard
- scoreboard keeps track of dependencies between instructions that have already issued
integer FU usually one clock ADD FU usually need more
Scoreboard - human abstraction
Instruction status
write the count of clock
- Issue in-order issue
- Read operation check Fj and Fk is yes
- Execution comp FU latency
- write result (write back) clean functional unit and register result status
Register result status
record functional unit that will update this register (destination register Fi)
why F0 to F30?
Functional unit status
FU: functional unit (module)
each functional unit has 9 status, which are
- Busy : indicate whether FU is using
- Op : which instruction is operating
- dest Fi : Rd (register destination) write status, Fs are all for read
- S1 Fj : Rs (first source register)
- S2 Fk : Rt (second source register)
- FU Qj : which functional unit are using j if Rj is No if waiting
- FU Qk : which functional unit are using k if Rk is No if waiting
- Rj : Yes or No Rj is usable by this FU
- Rk : Yes or No Rk is usable by this FU
life cycle of R is (No →) Yes → No(WAR →) execution start → after one cycle
Scoreboard Control Stages
every stage is one clock except FU execution
2.5. at execution start cycle, make F to No
3. execution complete
functional unit execute upon receiving operands (FU has latency of multi-cycle)
When the result is ready, it notifies the scoreboard that it has completed execution
- update noted remaining execution time
Why stall these stage?? - issue : structure hazard, WAW hazard (why we not stall WAW at read - since if next source operand has no dependency, scoreboard can make WAW) - read operation : WAR harard - write result : WAW hazard
Implications
solutions for WAR
stall writeback until registers have been read by reading registers only during read operands stage
solutions for WAW
detect hazard and stall issue of new instruction until other instriuction completes (no performance improvement) by Register result status
Limitation (of 6600 scoreboard)
- Do not distinguish dependency and hazard, so stall all of them
- No forwarding hardware
- each FU is limited to kind of instructions
- no register renaming
- do not issue on structural hazards (by limited number of FU)
- wait for WAR and prevent(not solved) WAW in ID
References
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