Register Scoreboarding

All three status is scoreboard and hardware fixed which has logical structure

functional unit status are book keeping in scoreboard

scoreboard keeps track of dependencies between instructions that have already issued

integer FU usually one clock ADD FU usually need more

Scoreboard - human abstraction

Instruction status

write the count of clock

Issue in-order issue

Read operation check Fj and Fk is yes

Execution comp FU latency

write result (write back) clean functional unit and register result status

Register result status

record functional unit that will update this register (destination register Fi)

why F0 to F30?

Functional unit status

FU: functional unit (module)

each functional unit has 9 status, which are

Busy : indicate whether FU is using

Op : which instruction is operating

dest Fi : Rd (register destination) write status, Fs are all for read

S1 Fj : Rs (first source register)

S2 Fk : Rt (second source register)

FU Qj : which functional unit are using j if Rj is No if waiting

FU Qk : which functional unit are using k if Rk is No if waiting

Rj : Yes or No Rj is usable by this FU

Rk : Yes or No Rk is usable by this FU

life cycle of R is (No →) Yes → No

(WAR →) execution start → after one cycle

Scoreboard Control Stages

every stage is one clock except FU execution

1. Issue

Done at first half of clock cycle

decode instructions, check for structural hazard

if FU not busy unconditionally issue one by one

FU to register result status

make busy

write FQR_ijk to FU status

2. read operation

read operands - wait until no data hazards(sufficient resource), then read operands

if registers are ready (all yes of F), then update to instruction status board

unconditionally go to execution and update time next to FU

exec - read = FU time

multi read is OK

2.5. at execution start cycle, make F to No

3. execution complete

functional unit execute upon receiving operands (FU has latency of multi-cycle)

When the result is ready, it notifies the scoreboard that it has completed execution

update noted remaining execution time

Why stall these stage?? - issue : structure hazard, WAW hazard (why we not stall WAW at read - since if next source operand has no dependency, scoreboard can make WAW) - read operation : WAR harard - write result : WAW hazard

4. Write Result

done at second half of clock cycle

Stall until WAR hazards by previous instructions

clean FU status and Register result status

remove other Q and make other F to Yes

Until all No(because of pre-instructions), next stage clean - after READ, WB OK

Implications

solutions for WAR

stall writeback until registers have been read by reading registers only during read operands stage

solutions for WAW

detect hazard and stall issue of new instruction until other instriuction completes (no performance improvement) by Register result status

Limitation (of 6600 scoreboard)

Do not distinguish dependency and hazard, so stall all of them

No forwarding hardware

each FU is limited to kind of instructions

no register renaming

do not issue on structural hazards (by limited number of FU)

wait for WAR and prevent(not solved) WAW in ID

References

IBM CDC 6600 scoreboard 에 대해.

scoreboard 음..어제 그 원리를 알았다! +_+; 물론 틀린것일수도 있다 ㅡㅡ;교수님께 아직 확인해보지 못했기에 ㅋㅋㅋ scoreboard 스코어보드...아마 번역하면 점수판이나 현황판쯤 되지 않을까? 그럼 점수판이나 현황판은 뭘 나타내는가? 생각을 해보자. 음..점수판은 경기도중 그때그때의 점수 상황을 나타낸다. 야구를 생각해보면 1회는 어느팀이 몇점 2회는 어느팀이 몇점 이렇게 경기의 흐름이랄까? 아니면 경기의 상태를 계속계속 적어놓는 거다.

https://blog.naver.com/PostView.nhn?blogId=ajunhyuk&logNo=40020965904&parentCategoryNo=&categoryNo=1&viewDate=&isShowPopularPosts=false&from=postView

/divider

/bread